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Whereas the Common Chiplet Interconnect Categorical (UCIe) normal for die-to-die interconnect is getting plenty of consideration, important work can also be being carried out on one other design entrance: digital half integration in chiplets. JEDEC, which joined palms with the Open Compute Challenge Basis (OCP) in late 2022 to standardize chiplet half descriptions by establishing a framework for the switch of expertise captured in an OCP-approved specification, has supplied particulars in regards to the first main consequence of this collaboration.
The 2 organizations have collectively introduced the combination of OCP’s Chiplet Knowledge Extensible Markup Language (CDXML) and JEDEC’s JEP30 PartModel Tips. They declare that integrating CDXML into JEP30 will present chiplet designers with standardized chiplet half descriptions electronically. “The combination of JEDEC JEP30 and OCP CDXML will create a unified platform that revolutionizes chiplet and digital half integration,” mentioned Michael Durkan, JEDEC Job Group Chair and PartModel Sponsor.
Determine 1 JEDEC and OCP have teamed as much as create an open chiplet economic system with a low barrier to entry.
In different phrases, it’ll open the door for automating system-in-package (SiP) design and meeting utilizing chiplets. Right here, chiplet descriptions embody essential data for SiP builders, together with thermal properties, bodily and mechanical necessities, habits specs, energy and sign integrity properties, and testing of in-package and safety parameters.
Because of this, part producers can create standardized digital half fashions that design engineers can simply use in quite a lot of digital programs. That, in flip, will result in a brand new, open chiplet economic system with a low barrier to entry.
OCP, based by Fb to drive open-source {hardware} innovation within the information middle ecosystem, goals to supply a collaborative platform for information middle and telecom operators, colocation suppliers, and enterprise IT customers. It earlier adopted the bunch-of-wires (BOW) chiplet interconnect expertise and has launched the Chiplet Design Change (CDX), an open-source working group working within the Open Area-Particular Structure (ODSA) sub-project.
Determine 2 Open Area-Particular Structure (ODSA) is a sub-project for growing a chiplet-based structure. Supply: OCP
The CDX group includes specialists from numerous fields, together with EDA, system design, IC and SiP design, OSAT, IC fabrication, and materials provide. It has just lately launched standardized chiplet fashions designed for the event and validation of 3D IC designs. That features machine-readable fashions for electrical and mechanical properties, which are actually a part of the JEDEC JEP30 PartModels.
JEDEC’s JEP30, half mannequin pointers to be used with EDA instruments, goals to ascertain the necessities for exchanging half information between half producers and their prospects for electrical and digital merchandise. The usual can outline a component in enough element to allow course of efficiencies throughout the half and product lifecycles.
JEDEC is an impartial semiconductor engineering commerce group and standardization physique that boasts lots of the world’s largest chip firms.
The mixture of OCP CDXML and JEDEC JEP30 requirements to specify chiplet fashions goals to put the muse of a chiplet design package (CDK). It would even be a big step towards a unified construction that helps each chiplets and basic digital elements throughout the overarching purview of JEDEC.
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