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Location: Bengaluru
Firm: Intel
Job Description
Growth and help of ASIC tech recordsdata and improvement of ASIC flows/methodologies. Enabling APR instruments for placement/routing and Timing to help new course of node. bodily designs (RTL to GDSII) of check autos to guage developed tech file and APR circulation/methodology. Common Interplay with Stakeholders together with distributors throughout techfile and circulation improvement. Well timed monitoring of points and resolving buyer help points. Write good paperwork for ASIC flows and PDK. Prepare the customers and design engineers on ASIC flows and tech file utilization. Debug the complicated design points and assist the design and CAD groups in PDK and circulation deployments.
{Qualifications}
BTech/BE/MTech/ME/MSc in Electronics/Pc science with Business expertise in ASIC PDK package/Bodily design/ ASIC Design automation function.Palms-on expertise with Synopsys and Cadence Place and Route instruments, Timing instruments, Ground planning, IR Drop and Bodily verification. Ought to have good understanding of Verilog/VHDL. Publicity to low energy methods and PPA evaluation. Data of tcl and perl scripting is a should. Sturdy presentation and communication abilities inside a global atmosphere. Group oriented in parallel to capacity to work independently and convey new initiatives. Good in stakeholder administration and ought to be detailed oriented.
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