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Through the manufacturing course of, chipmakers spanning logic, reminiscence and specialty gadgets attempt to predictably create good die at quantity with nanoscopic precision. On the identical time, they attempt to get probably the most die out of a wafer on the lowest price. It’s not straightforward, and our expertise means that, as chips scale to smaller geometries, it’s solely getting tougher.
Contending with the rounded or slanted space on the wafer perimeter, generally known as the bevel (Determine 1), has been particularly problematic. As layers upon layers are etched to create tiny buildings and kind next-generation die, the sometimes clean bevel floor can change into pitted or tough, and movies or processing residue can accumulate.
In subsequent steps, these byproducts can typically flake off and migrate to energetic areas of the wafer—doubtlessly inflicting defects and impacting the flexibility to yield defect-free uniform die.
Historical past reveals that as reminiscence and logic evolve, these challenges compound. Supplies used to provide superior logic and 3D NAND circuitry have generated extra byproducts and have larger vulnerabilities; additional, wafer-bond packaging methods place stringent new necessities on bevel flatness and uniformity.
Over the previous 15 years, chipmakers have sought to deal with these bevel-related points whereas additionally maximizing the obtainable space on a wafer from which to create usable chip dies. The appearance of immersion lithography methods within the 2000s elevated the significance of wafer edge integrity as a result of the liquid immersion course of is vulnerable to propagation of defect-causing materials.
In immediately’s advanced manufacturing surroundings, growing die yield is a tough however crucial step to assist chipmakers maximize fab productiveness and ship superior gadgets affordably.
One widespread method in recent times has been bevel etch cleansing, significantly in forming issues like shallow trench isolation (STI) buildings and call holes. Lam Analysis’s bevel etch cleansing has since been utilized in many strategic factors alongside the fab line, resembling post-etch, pre- and post-deposition, and pre-lithography. These measures have confirmed efficient at decreasing defect-causing accumulation and boosting machine yield as much as 0.2-0.5% per step—a major achieve in a high-volume, modern manufacturing surroundings. Further advantages embrace larger yield stability and ever-smaller edge exclusion zones.
Bevel etch: Obligatory however not sufficient
Whereas bevel cleansing continues to be obligatory, new challenges are rising as architectures advance. For instance, the lengthy moist etch processes used for top facet ratio 3D NAND trenches require chemistries that always trigger extreme pitting and injury to the bevel.
Superior logic gadgets that use intermediate back-end-of-line (iBEOL) metallic interconnects for native routing as a part of 3D sequential integration methods (resembling CMOS-over-CMOS) additionally pose new challenges, as a result of metallic traces of copper, tantalum or different supplies intrude into the bevel space. Bevel cleansing could be helpful—however restricted—as it will possibly’t defend towards undesirable migration of the smallest metallic particles.
As well as, broadening adoption of 3D packaging methods that make the most of wafer bonding locations very tight restrictions on movie variation and profile roll-off on the wafer perimeter, together with the bevel, to forestall yield loss within the bonding course of. The formation of voids, non-hermeticity, and lowered bonding power have been recognized as points within the MEMS sector, the place wafer bonding is broadly used however geometries are much less demanding.
The appearance of bevel deposition
Happily, a brand new approach of addressing these challenges has emerged: selective PECVD deposition of a exactly managed, tunable dielectric movie on the bevel (Determine 2). Amongst different benefits, one of these deposition course of provides a layer of safety previous to demanding processing steps (like prolonged moist etch), considerably reduces roughness and flatness variation, and reduces contamination and injury threat by encapsulating advanced movie stacks and their uncovered interconnect supplies on the bevel.
One other plus is the flexibility to mix frontside and bottom deposition right into a single-step course of. That is extremely fascinating for high quality, time, and financial causes, however inconceivable with many SiO2 deposition or progress processes.
Main chipmakers have already carried out bevel deposition in superior fabs around the globe. It’s proving to be a game-changer by driving extra predictable manufacturing and simplifying 3D integration. Anne Roule, head of the semiconductor platform division at CEA-Leti, not too long ago famous that this “drives considerably larger yield and permits chipmakers to undertake breakthrough manufacturing processes” that have been beforehand unfeasible. Using this bevel-specific expertise can cost-effectively increase line and packaging yield considerably throughout the wafer move.
Attaining these ends in a high-volume surroundings requires consideration to many elements, together with safety of the wafer’s energetic space throughout bevel deposition. The movie stacks utilized in iBEOL and different kinds of multilayer interconnect have more and more tight thermal budgets (another excuse conventional thermal oxide processes aren’t appropriate for bevel deposition) and are inclined to wreck.
Exact management of the plasma within the bevel space is important. One efficient method is the usage of a toroidal plasma with plasma exclusion zone (PEZ) confinement rings in a number of sizes, which permit correct shaping of the plasma for optimum ends in a extremely managed area, together with as much as 4 mm of the outer fringe of the wafer’s back and front sides.
The final word consideration is the deposited movie itself, as excessive levels of composition flexibility and bodily profile tunability are necessary enablers for engineers who must tailor options for his or her particular conditions. Revealed analysis on iBEOL bevel deposition has proven {that a} SiH4-based, oxide-rich silicon oxynitride movie affords a powerful mixture of purity, wet-etch resistance, bonding edge high quality, and safety from metallic contamination, and “open[s] the best way to course of[ing of] advanced stacked wafers with numerous supplies in a stringent FEOL surroundings.”
Leads to logic, reminiscence and packaging
Shut collaboration with chipmakers and expertise companions like CEA-Leti has been crucial in Lam’s growth of revolutionary bevel options that drive extra stability within the manufacturing course of. Utilizing these bevel deposition and bevel-etch methods has enabled semiconductor producers operating greater than 100,000 wafer begins per 30 days to yield doubtlessly hundreds of thousands of additional die—which may very well be price tens of hundreds of thousands of {dollars}—over the course of a yr.
In accordance with Hideshi Miyajima, a expertise govt of reminiscence course of at Kioxia, the adoption of bevel deposition in Kioxia’s manufacturing course of is proving important to “enhancing high quality within the manufacturing course of” and in its “capacity to offer next-generation flash reminiscence at scale to [Kioxia’s] prospects.”
Use of selective PECVD deposition methods on the wafer perimeter has been proven to considerably increase machine and packaging yield for superior gadgets presently in manufacturing.
Wanting forward, the present outcomes counsel that this added stage of wafer bevel management and administration could assist decrease yield threat throughout broader introduction of recent and extremely demanding 3D interconnect and packaging applied sciences on the 5-nm and 3-nm course of generations and past.
—Jack Chen is director of engineering at Lam Analysis.
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